1. Technical Field
The present invention generally relates to logic circuits used in integrated circuit devices, such as microprocessors, memory chips and the like. More specifically, an efficient, Exclusive-Or complementary metal oxide semiconductor (CMOS) logic gate is provided that consumes less power and switches faster than conventional Exclusive-Or (XOR) gates.
2. Description of Related Art
Typically, XOR gates are slow, large, power hungry and complex devices when compared to other basic gates having the same number of inputs. Further, these problems are compounded since multiple XOR gates are often connected together in a "tree" configuration.
A conventional CMOS XOR gate is illustrated in FIG. 4. Ten (10) transistors are included in the gate. That is, P-type devices (PMOS transistors 1, 2, 3, 4 and 9) are included and will be in a "turned on" state (where they will conduct electrical current) when a logical "0" (absence of a voltage) is present at their gates. N-type devices (NMOS transistors 5, 6, 7, 8 and 10 are also included and will be in a "turned on" state when a logical "1" (a voltage, i.e. Vdd) is present at their gates. Transistors 9 and 10 make up an inverter circuit which provides a complementary signal output, i.e. a strong logical 1 (Vdd) or logical 0 (ground potential) which can also be transmitted to another interconnected logic device.
Those skilled in the art understand that the power consumption of a transistor is roughly proportional to its physical size. For example, a transistor with a 10 micron width will use about twice as much power as a transistor with a 5 micron width. In the prior art circuit of FIG. 4 if it is assumed that transistors 5-8 have a 10 micron width, then the PMOS transistors 1-4 will need to be of an approximately 20 micron width in order to get equivalent drive capability (PMOS transistors need to be at least twice as large as equivalent NMOS transistors to get the same output drive). This gives a 5 micron output drive strength, compared to a required 30 micron input loading. Thus, the combination of ten (10) transistors and five (5) of those being large PMOS devices causes the XOR gate of FIG. 4 to be a very large circuit in relation to its drive strength.
Since XOR gates are often connected in a tree configuration, such as parity or other error checking/correcting circuits, the circuit of FIG. 4 would also take up a substantial amount of area on the chip, or integrated circuit (IC), due to the large transistor sizes. The large "fan-out" causes the circuit of FIG. 4 to be relatively slow, particularly when compared to the high speed clock frequency of today's microprocessor designs (excess of 100 MHz). Further, the large size of the devices of FIG. 4, coupled with the fan-out creates a large amount of capacitance that must be switched. This in turn causes the power consumption to be high and the circuit to switch relatively slowly.
The XOR gate of FIG. 4 is a static device, which means that the actual input logic signals will cause the circuit to switch, and that there are no set/reset signals required, i.e. no separate clock signals need to be input to the circuit. Conversely, dynamic circuits require that a set or reset signal be input and further necessitate the need for additional set or reset logic which complicates the design of a system.
Dynamic XOR gates are known in the art. These types of gates typically minimize the number of PMOS transistors which are needed. Further, dynamic XOR gates can be smaller and faster than equivalent prior art static XOR gates. However, these dynamic circuits require synchronized inputs and potentially switch twice during a single clock transition cycle, thereby consuming a considerable amount of power. Additionally, the required reset circuits will take a substantial amount of time to design and tune. Thus, dynamic XOR circuits require increased design time (due to their complexity), large amounts of electrical power, and potentially greater area on the chip (due to the additional reset circuitry) making them a less than desirable alternative to static XOR gates.
Thus, it can be seen that a need exists for a low power, fast, static XOR gate that can be used in many places throughout an integrated circuit device.